1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more specifically to a method of manufacturing a semiconductor device improved in a step of forming a transition metal silicide layer in self-aligned manner on an impurity diffusion layer of a semiconductor substrate.
2. Description of Related Art
Along with the development for the integration degree and the performance of semiconductor devices such as LSIs, the lateral width of a gate electrode has been reduced to less than quarter micron in MIS transistors. In such a fine device structure, it is essential to decrease the depth of an impurity diffusion layer at the same time with the reduction of the lateral width of the gate electrode for decreasing the short channel effect and ensuring the source-drain withstand voltage. As an example, in a MIS transistor having 0.25 .mu.m lateral width of the gate electrode, it has been demanded to shallow the depth of the impurity diffusion layer to less than about 0.08 .mu.m (80 nm).
As the depth of the impurity diffusion layer is made shallower, a sheet resistance value in a source-drain region increases to result in a problem of lowering a response speed and an operation limit frequency of the semiconductor device. This is because the operation limit frequency of the MIS transistor is in an inverse proportion with a gate delay time. This phenomenon gives a significant problem, particularly, in a microprocessor requiring high speed operation.
As a countermeasure, a salicide self aligned silicide process of forming a transition metal silicide layer of low resistivity on a source-drain region has been proposed. The outline of this process is to be explained below with reference to FIG. 7 and FIG. 8.
FIG. 7 and FIG. 8 are schematic cross sectional views illustrating a production process of MOSIC using an existent salicide process. At first, as shown in FIG. 7A, a device isolation region 2 is formed on a semiconductor substrate 1 made of silicon. After forming a thermal oxidation film and forming a polycrystal silicon layer patterning is applied to form a gate oxide film 3 and a gate electrode 4 and, further, impurities are injected shallowly by ion implantation.
Then, as shown in FIG. 7B, after forming a thick silicon oxide layer over the entire surface it is etched back to form side wall spacers 5 on the lateral sides of the gate electrode 4. Subsequently, impurities are again ion implanted and an activating heat treatment is applied to form an impurity diffusion layer 6 of an LDD structure.
Then as shown in FIG. 7C, a transition metal layer 7 such as made of Ti is formed over the entire surface and the transition metal layer 7 on the impurity diffusion layer 6 is selectively converted into TiSi.sub.x through solid phase diffusion by applying a first heat treatment at about 600.degree. C. Under the first heat treatment condition, the transition metal layer 7 does not react with the silicon oxide material. If the transition metal layer 7 is formed with the surface of the polycrystal Si gate electrode 4 being exposed, TiSi.sub.x is formed also on the gate electrode 4. However, if a spacer such as made of silicon oxide is formed on the gate electrode 4, TiSi.sub.x is not formed on the gate electrode 4.
Then, unreacted transition metal layer 7 is removed by wet etching with aqueous ammonia-hydrogen peroxide (mixed aqueous solution of NH.sub.3 and H.sub.2 O.sub.2) to leave TiSi.sub.x on the impurity diffusion layer 6. Subsequently, TiSi.sub.x of the impurity diffusion layer 6 is converted into TiSi.sub.2 by a second heat treatment at about 800.degree. C., to form a transition metal silicide layer 8. This shown in FIG. 8A. In the figure, the transition metal silicide 8 is formed also on the gate electrode 4.
A main portion of the salicide process is as described above. Subsequently, an interlayer insulation film 9 is formed and a connection hole 10 facing the impurity diffusion layer 6 is opened by a customary method. Then, a Ti/TiON/Ti laminate structure layer and an Al type metal layer are formed and patterned to form an adhesion layer/barrier metal layer 11 and an Al layer 12, to complete MOSIC.
The MOSIC using the salicide structure has an advantage of lowering the source/drain resistance by about one digit compared with similar type of existent MOSIC. However, along with the recent trend of reducing the size of devices, the exposed surface area for the impurity diffusion layer 6 has also been made finer. If the salicide process is applied to such a narrow region of the impurity diffusion layer, crystal grains of the transition metal silicide are agglomerated to roughen surface and, as a result, lowering of the sheet resistance of the transition metal silicide layer can not be attained.
Further, it is also necessary to decrease the film thickness of the transition metal silicide layer corresponding to the decreasing depth of the impurity diffusion layer. The decreased thickness of the transition metal silicide layer also tends to cause agglomeration of the crystal grains. Accordingly, when a thin transition metal silicide layer is formed on a narrow region of the impurity diffusion layer, it is demanded for the development of a salicide process capable of preventing the crystal grains from agglomeration and attaining a smooth surface stably.
It is considered that one of the causes for the agglomeration of crystal grains in the transition metal silicide layer is attributable to a not uniform native oxide film present inevitably on the surface of the impurity diffusion layer. Among transition metal silicides, titanium silicide having the lowest resistance (resistivity: 15 .mu..OMEGA..multidot.cm) and used most frequently includes two types of crystal structures, namely, C49 crystal structure as a low temperature stable phase and C54 crystal structure as a high temperature stable phase. The C54 crystal structure is low resistance and stable TiSi.sub.2. The C49 crystal structure causes phase transformation into the C54 crystal structure by a heat treatment at about 900.degree. C., in which it is recrystallized accompanying grain boundary diffusion. Volumic shrinkage occurs in this stage and agglomeration of the crystal grains is observed. If the not uniform native oxide film remains on the impurity diffusion layer, agglomeration is promoted to result in roughening on the surface of the transition metal silicide.
As a pretreatment for forming the transition metal layer, light etching with a dilute aqueous HF solution is usually applied. However, it has been reported that complete removal of the native oxide film in a fine opening by the wet treatment is extremely difficult, for example, in the Pretext of 21th Super LSI Ultra Clean Technology Symposium; p156 (1994).
Further, even if the native oxide film is completely removed by the wet treatment, a not uniform native oxide film is formed again in the step of the subsequent drying treatment. As described above, when the transition metal layer is formed and subjected to the heat treatment with no sufficient cleaning for the surface of the impurity diffusion layer, siliciding reaction proceeds not uniformly. It is considered that the silicides tend to recrystallizate for stabilization in the succeeding second heat treatment to cause agglomeration.
As a pretreatment in place of the wet treatment for removing the native oxide film, it has been reported a method of the cleaning the surface of the impurity diffusion layer by an inverse sputtering in a Ti sputtering device or the like, for example, in IEEE Transactions on Electron Device 38-1, p88 (1991). In this method, inverse sputtering is applied by using Ar gas in a parallel plate sputtering device capable of generating plasmas at a density in the order of 1.times.10.sup.10 /cm.sup.3 by combined use of magnetic fields. Since the transition metal layer can be formed immediately after the cleaning for the surface of the impurity diffusion layer by this in-situ cleaning, there is no worry for the agglomeration of the transition metal silicide.
However, for completely removing the native oxide film by the parallel plate type device, it is necessary to apply an acceleration voltage of higher than 1 KV to Ar.sub.+. Accordingly, the surface of the impurity diffusion layer is roughened by the incident Ar.sub.+ ion energy or crystal defect or like other damage is caused to make the progress of the subsequent siliciding reaction not uniformly thereby bring about a problem of increasing stresses in the silicide layer and causing peeling. Further, since extended portions of gate electrode-wirings are exposed to ion incidence at a high acceleration voltage upon sputter etching, the thin gate oxide film suffers from plasma damages.